16717_4.E-R Model16717_Cocncurrency To be followed12316717_Data Models16717_Lecture 12 Part116717_Lecture 13,1416717_Lecture 15-lectue1916717_lecture1-2_ch1-introduction16717_lecture3-3_ch2-Architecture n Models16717_lecture4-4_ch3-hierarchial model16717_lecture4-5_ch4-network model16717_lecture5-6_ch5-ER Diagram16717_lecture9_10_ch7-SQL16717_normalizationprateekbhatia16717_Relational Algebra Model16717_Transaction management to be Followed
Showing posts with label #3sem #4sem. Show all posts
Showing posts with label #3sem #4sem. Show all posts
AC-Initial valueALL CKTs - Combinational Logic DesignArithmetic shift RIGHT and LEFT
BCD32
DHT-pmpDigitalNotesFF notes
K-MAPS
L-1 Introduction, FlipFlops
L-2 Registers
L-3 Decoder, Demux, Mux, Encoder
L-4 Fixed Point Representation
L-5 Floating Point Representation
L-6 Register Transfer Language
L-8 Binary Adder, Subtractor
L-9 Bus Transfer, Memory Transfer
L-10 Logic Microoperations
L-11, 12 Shift Microoperations, ALU
L-13,14 Instn codes, Common bus sys
L-15 compu instr
L-16 Timing and Control
l-17 Instruction cycle-fetch n decode
L-18 flowchart for instruction cycle
L-19 Memory Ref instrn
L-20 Input-Output n Interrupt
Lecture 19 Computer Design desc
Lecture 20 CU ImplementationLecture
21 Design of C
Lecture 22 CPU- General Reg Org
Lecture 23 Stack Org
Lecture 24 Three-Two-One Address inst
Lecture 25 Addressing Modes
Lecture 26 Data transfer manipulation
Lecture 27 Prog control
Lecture 28- RISC & CISC
Lecture 34- Input-Output interface
Lecture 35- Asynchronous transfer mode
Lecture 36-Asynchronous transfer mode-II
Lecture 37
Lecture 38
Lecture 39
Lecture 40- ch12-Memory Org
Lecture 41
Lecture 42
Lecture 43
Lecture 44
Lecture 46-Ch9-Parallel processing
Lecture 47
Lecture 48Memory Organization
